This invention relates generally to semiconductor integrated circuits, and more specifically to bipolar integrated circuit (IC) cell or array structures and methods.
Integrated circuit technology has made significant progress over the last forty years. Integrated circuits are now manufactured at much lower costs, with lower power consumption, higher speeds, and smaller sizes. The number of devices manufactured on a single chip exceeded the generally accepted definition of very large scale integration (i.e., more than 100,000 devices per chip) in the mid-1970's. By 1986 this number had grown to over 1 million devices per chip, and by 2000 had exceeded 1 billion devices per chip.
The production of a new integrated circuit begins with a design phase, where the desired functions and necessary operating specifications are initially determined. IC designers create devices from the top down by first identifying large functional blocks. Next, sub-blocks are defined, and finally, logic gates necessary to implement the sub-blocks are selected. Each logic gate is designed by appropriately connecting devices that are ultimately slated for fabrication on semiconductor wafers.
Designers then lay out the circuit, which consists of sets of patterns that correspond to device regions or interconnect structures. Such patterns are sequentially transferred to wafers as part of a wafer fabrication process sequence (e.g., using photolithographic techniques).
As part of a chip design process, designers must select a process technology to produce the device structures that make up a circuit. Such process technologies include CMOS, bipolar, or BiCMOS process technologies. Chip designers typically choose a process technology depending upon specific application requirements including cost, packaging constraints, heat dissipation, switching speeds, power consumption, and noise immunity.
Although logic families based on bipolar process technology are among the most mature in the semiconductor industry, bipolar processing technology continues to be refined to meet growing challenges of speed, lower delay-power product, and higher levels of integration. Such refinements challenge bipolar integrated circuit designers as they strive to produce next generation semiconductor chips in a timely and cost effective manner.
During the layout phase, designers often utilize libraries of standard cells, which comprise for example, reconfigurable arrays of transistors and resistors, to create or generate a particular circuit layout. One problem with prior art bipolar cells or reconfigurable arrays is that they often have wasted space, which impacts density, overall chip size and cost. Additionally, typical prior art bipolar cells have complicated and uneven routes for coupling devices together, which can result in interconnect resistance and capacitance problems. In addition, prior art bipolar cells are not optimized for performance and matching over a wide variety of processes.
Accordingly, a need exists for configurable bipolar cells or arrays that are optimized for density, ease of use, ease of routing, maximum performance, versatility and sensitivity to process variation.